The present invention relates to a semiconductor device, and more particularly to a semiconductor device with a three-dimensional complementary metal oxide semiconductor inverter.
The three-dimensional complementary metal oxide semiconductor (3-D-CMOS) inverter is discussed in J. F. Gibbons, One-Gate-Wide CMOS Inverter on Laser-Recrystallized Polysilicon. This 3-D-CMOS inverter will briefly be described referring to FIG. 1.
As shown in FIG. 1, a field oxide film 2 is formed on a substrate 1. P.sup.+ type drain and source regions 3 and 4, are formed in each of the island regions (i.e., element regions) of the substrate 1, which are electrically isolated by the field oxide film 2. The drain and source regions 3 and 4 are also electrically isolated. A first gate oxide film 5 is formed on the island region which includes a channel region between the source region 3 and drain region 4. A gate electrode 6 is formed on the first gate oxide film 5. It is made of polysilicon and has a thickness of, for example, 1 .mu.m. It is used as the parts of both a p-channel and an n-channel MOS transistors. A second gate oxide film 7 is formed on the gate electrode 6. An active layer 8 is formed on the oxide film 7. It consists of an n.sup.+ type source region 9, an n.sup.+ type drain region 10, and a p type channel region 8' sandwiched between the n.sup.+ type regions 9 and 10. The active layer 8 is formed in the following manner. First, polysilicon is deposited on the entire surface of the unfinished product, thus forming a polysilicon film. Ions of p-type impurity are implanted into the polysilicon film. This film is irradiated with an Argon laser beam is applied from a scanning type continuous wave (cw) argon laser to this film, thereby recrystallizing the film. Then, the recrystallized film is patterned, thus forming a p type layer. Finally, ions of n type impurity are implanted into the end portions of this p type layer, thus forming the active layer 8.
The field film 2, p.sup.+ type region 3, 4, oxide film 7 and the active layer 8 are covered by an insulation film 11. The insulation film 11 has contact holes 12. Al wiring strips 13, 14 and 15 are formed on the insulation film 11. The strip 13 is connected through the contact hole 12 to the p.sup.+ type source region 3. The strip 14 is connected through the contact 12 to the n.sup.+ type source region 9. The strip 15 is connected through two contact holes 12 to the p.sup.+ type drain region 4 and n.sup.+ type drain region 10.
FIG. 2 is the equivalent circuit diagram of the 3-D-CMOS inverter described above. This circuit comprises a p-channel MOS transistor Tr1 and a n-channel MOS transistor Tr2. The transistor Tr1 is made of the source region 3 and the drain region 4, the oxide film 5 and the gate electrode 6. The transistor Tr2 is made of the n.sup.+ type regions 9 and 10, oxide film 7 and gate electrode 6. The gate electrode 6 is connected to a Vin terminal. The Al wiring strip 13 is connected to a terminal V.sub.DD, and the Al wiring strip 14 to V.sub.SS. The Al wiring strip 15 is connected to a terminal Vout.
As mentioned above, the conventional 3-D-CMOS inverter shown in FIG. 1 has an active layer 8 which consists of an n.sup.+ type source region 9, an n+ type drain region 10, and a p type channel region 8' sandwiched between the n.sup.+ type regions 9 and 10. The active layer 8 is formed, as mentioned above, by depositing polysilicon on the entire surface of the unfinished product, thus forming a polysilicon film, by implanting ions of p-type impurity into the polysilicon film, by irradiating this film with A laser beam applied from a scanning type continuous wave (cw) argon laser, thereby recrystallizing the film, by patterning the recrystallized film, thus forming a p type layer, and by implanting ions of n type impurity into the end portions of this p type layer. The active layer 8 thus formed is not a perfectly single crystal layer: it is rather a polysilicon layer. The effective mobility of the n-channel MOS transistor Tr2 having this layer 8 is smaller than that of the n-channel MOS transistor formed on the single crystalline silicon substrate. In this respect, the 3-D-CMOS inverter of FIG. 1 operates but at a low speed.
To increase the operating speed of the inverter, the channel of the inverter has been broadened by increasing the area of the active layer 8. This method, however, induces another problem that the larger the layer 8, the more bulky the 3-D-CMOS inverter. The packing density of a semiconductor device using the 3-D-CMOS inverters is inevitably low.